2040PCS IC's AMD # PALCE22V10H-15JC/4
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24-Pin EE CMOS (Zero Power) Versatile PAL Device
As fast as 5-ns propagation delay and 142.8 MHz f
10 macrocells programmable as registered or combinatorial, and active high or active low to
Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)
Global asynchronous reset and synchronous preset for initialization
Power-up reset for initialization and register preload for testability
Extensive third-party software and programmer support
24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC
5-ns and 7.5-ns versions utilize split leadframes for improved performance
The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and
flip-flops at a reduced chip count.
The PALCE22V10Z is an advanced PAL
device built with zero-power, high-speed, electricallyerasable
CMOS technology. It provides user-programmable logic for replacing conventional zeropower
CMOS SSI/MSI gates and flip-flops at a reduced chip count.
The PALCE22V10Z provides zero standby power and high speed. At 30 μA maximum standby
current, the PALCE22V10Z allows battery-powered operation for an extended period.
The PAL device implements the familiar Boolean logic transfer function, the sum of products. The
PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed
the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each
macrocell can be programmed as registered or combinatorial, and active-high or active low. The
output configuration is determined by two bits controlling two multiplexers in each macrocell.
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